Synopsys, announced it has broadened its ongoing academic collaboration by entering into an agreement to license novel digital synthesis technologies from EPFL, the Swiss Federal Institute of Technology in Lausanne, Switzerland.
Over the past two years, Synopsys has been working in partnership with the University of Rochester and Yokohama National University developing a complete digital circuit design flow for Superconducting Electronics (SCE). This work is being conducted under IARPA’s SuperTools project, a multi-year research effort that aims to create a SCE circuit design flow by developing a comprehensive set of Electronic Design Automation (EDA), and Technology Computer Aided Design (TCAD) tools to enable the analysis and design of SCE circuits with Very-Large-Scale Integration (VLSI).
HR Technology News: TecHRseries Interview with Michelle Boockoff-Bajdek, CMO at SkillSoft
EPFL’s Integrated Systems Laboratory (LSI) has developed a method that may reduce the power requirement of electronic chips by mapping out their logic flows in a novel way. By deploying a different set of logic functions for the gates on the potentially billions of transistors found in modern electronic circuits, this system may shorten the circuits’ calculation steps. This shortening may enable chip designers to make their chips faster or more energy efficient. EPFL’s LSI is applying these methods in ongoing research on SCE conducted under NSF’s SuperCool project.
HR Technology News: DHGE Launches Resilience Program for COVID-19 Frontline Workers
Traditionally, four basic logic functions (and-or-not-mux) have been used to realize electronic circuits. But, EPFL’s LSI group set out to produce optimized digital circuits by radically changing the software that generates logic diagrams involving majority functions. Initial studies indicated that the new approach could reduce the number of logic steps needed to execute a given task. Later experiments confirmed that these optimizations were able to reduce the number of logic levels by 18% on average. Engineers can exploit the reduction in logic levels to create faster or less power-hungry chips.
HR Technology News: Censia Talent Intelligence Platform Now An SAP Endorsed App Available On SAP App Center