The online courses are offered on edX.org and will make RISC-V training more accessible
The Linux Foundation, the non-profit organization enabling mass innovation through open source, and RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), have announced the release of two new free online training courses to help individuals get started with the RISC-V ISA. The courses are available on edX.org, the online learning platform founded by Harvard and MIT.
“RISC-V International is committed to providing opportunities for people to gain a deeper understanding of the RISC-V ISA and expand their skills,” shared Calista Redmond, CEO, RISC-V International. “These courses will allow everyone to build deeper technical insight, learn more about the benefits of open collaboration, and engage with RISC-V for design freedom.”
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With the recent market momentum of RISC-V cores, systems-on-chips (SoCs), developer boards, and software and tools across computing from embedded to enterprise, there is a strong community need to empower individuals who understand how to implement and utilize RISC-V. In order to help meet that demand, The Linux Foundation and RISC-V International designed these free online courses to significantly reduce the barrier to entry for those interested in gaining RISC-V skills.
The first course, Introduction to RISC-V (LFD110x), guides participants through the various aspects of understanding the RISC-V ecosystem, RISC-V International, the RISC-V specifications, how to curate and develop RISC-V specifications, and the technical aspects of working with RISC-V both as a developer and end-user. The course provides the foundational knowledge needed to effectively engage in the RISC-V community, contribute to the ISA specifications, and develop a wide range of RISC-V software and hardware projects. Introduction to RISC-V was developed by Jeffrey “Jefro” Osier-Mixon, program manager for RISC-V International, and Stephano Cetola, technical program manager for RISC-V International.
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The second course, Building a RISC-V CPU Core (LFD111x), focuses on digital logic design and basic central processing unit (CPU) microarchitecture. Using the Makerchip online integrated development environment (IDE), participants will implement technologies ranging from logic gates to a simple and complete RISC-V CPU core. The class will allow participants to familiarize themselves with a variety of emerging technologies supporting an open source hardware ecosystem, including RISC-V, transaction-level verilog, and the online Makerchip IDE. Building a RISC-V CPU Core was developed by Steve Hoover, founder of Redwood EDA.
Enrollment is now open for Introduction to RISC-V and Building a RISC-V CPU Core. Auditing each course through edX is free for seven weeks, or you can opt for a paid verified certificate of completion, which provides access to the course for a full year and additional assessments and content to deepen their learning experience.